module ledw(clk,led,rst,state);
input clk,rst;
output [11:0] led;
output [1:0] state;
reg [1:0] state;
parameter s0=2'b0,s1=2'b1,s2=2'b10,s3=2'b11;
reg [11:0] led=12'b0000_0000_0001;
always @ (posedge clk)
begin
	if(!rst)
		begin led<=12'b0000_0000_0001; state<=s0; end
	else
	case(state)
	s0:begin
		if(led[11]==1'b1) begin state<=s1;end
		else led[11:0]<={led[10:0],led[11]};
	end
	s1:begin
	if(led[0]==1'b1) begin state<=s2; led<=12'b1000_0000_0001; end
	else led[11:0]<={led[0],led[11:1]};
	end
	s2:begin
		if(led[6:5]==2'b11) begin state<=s3;end
		else begin 
		led[5:0]<={led[4:0],led[5]};
		led[11:6]<={led[6],led[11:7]};
		end
	end
	s3:begin
		if(led[11:0]==12'b1000_0000_0001) begin state<=s0; led[11:0]<=12'b0000_0000_0001;end
		else
		begin
			led[5:0]<={led[0],led[5:1]};
			led[11:6]<={led[10:6],led[11]};
		end
	end
	default:
	state<=0;
	endcase
end


endmodule